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SAMSUNG FOUNDRY

10nm FinFET and multi-patterning technology – Evolution Continues

Full process optimization – Both patterning technology and FinFET transistor performance
Full process optimization – Both patterning technology and FinFET transistor performance
10nm will be the last practical node to utilize conventional optical lithography technology, even with multi-patterning methodology. Samsung foundry has maximized utilization of multi-patterning technology to overcome the cost concern and 10nm will be another long-lived node like as 14nm. To support long life time, transistor performance has been boosted with optimization of fin structure and stress engineering
After successful offering of 14nm FinFET technology, Samsung foundry has developed 10nm FinFET technology with more optimized fin structure and cost effective multi-patterning technology to meet aggressive market requirement.

The real benefit of 10nm technology is not just on process optimization, but also DTCO methodology. With competitive design rule and innovation, 2nd Gen SDB(Single Diffusion Break), competitive standard cell library with bi-directional routing, and special structure to enable compact layout are enabling more competitive area scaling with cost effective and better performing technology.

In order to support long-lived technology, design enablement and IP optimization has been built by collaborating with ecosystem partners. Collaboration specifically around optimal Fin-based design infrastructure and advanced IP development on top of 14nm learning has resulted in more competitive foundation libraries and advanced IP suite.
Samsung’s 10nm FinFET Process Offering – 10LPE/10LPP/10LPU
10LPE(early Edition) targets the early technology leaders and time-to-market customers with such as mobile application SoCs to meet the latest mobile gadgets’ aggressive schedule and improved performance/power requirement than 14nm. Foundry industry first mass production had started based on 10LPE with successful ramp up to support customer’s product roadmap.

10LPP(Performance boosted version) is the 2nd generation 10nm FinFET technology with performance enhancement by 10% than 10LPE. Like as other FinFET technology, 10LPP is also single platform to cover wide application from high performance computing to low power mobile. 10LPP will be the right solution for 2018 or afet mass production.

10LPU is successful output of DTCO(Design Technology Co-Optimization) to offer more scalability and better performance than prior 10nm nodes. Technology qualification is scheduled at Sep., 2017.
10LPE Early time to market edition 10LPP Performance Boosted Edition 10LPU DTCO beneficial edition
10LPE/LPP are ready for product T/O
10nm FinFET process technology features
- Optimized Power/Performance/Area benefits
- Full work function controlled device flavors
- Evolved 2nd Gen SDB(Single Diffusion Break)
- Design innovation for compact layout
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