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SAMSUNG FOUNDRY

Design Service

Accelerate your business success with unparalleled Samsung Design Services.
Complementing its high-volume manufacturing expertise, Samsung has regional foundry design services teams to work with customers on a local level. Samsung’s design team work side-by-side with the customer internal design team throughout the entire process, helping to mitigate any issues that might come up once the product goes to tape-out and, evidentially, to volume manufacturing. Early engagement design services are available at SAMSUNG design centers and through its partner network. Foundry customers can also take advantage of worldwide on-site design services.

Samsung support various Design Service Model

Samsung Samsung Customer Customer Both Both
Service Items Library
(Foundation)
IP
(Supplier)
IP
(3rd party)
Design Flow
/ Sign-off
DFT Physical
Design
Physical
Verification
EDS
Test
Package
/ Test
Turn Key
Foundry
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Samsung Samsung Samsung Samsung Customer Customer Customer Samsung Samsung
Samsung Samsung Customer Both Customer Customer Customer Samsung Samsung
Samsung Samsung Customer Customer Customer Customer Customer Customer Customer
Customer Both Customer Customer Customer Customer Customer Customer Customer
PPA Analysis
Power Performance Area(PPA) analysis is one of the special service from Samsung Foundry. For the design of next generation technology, a customer may want to identify the best trade-offs between power, performance and area. Design complexity now demands that all aspects of the design be co-optimized. Thus, Samsung Foundry provides the PPA analysis service using Samsung design infra to help to see the best results. Base on this analysis report, the customer can estimate the competitiveness of next product, as well as, he/she can experience a total solution from the product development to the mass production. Samsung can provide a full range of PPA analysis services - standard cell libraries and memory models - Samsung design methodologies for the physical implementation and sign-off - power report based on required PVT conditions - speed report – physical size report.
If you require our ‘PPA Analysis’ consultation service, please contact your Account Manager.
Low Power Design
In recent years, power is being given comparable weight to area and speed considerations. The most visible driving factor has been the remarkable success and growth of the portable consumer electronics market. Even when power is available in non-portable applications, the issue of low-power design is becoming critical. Up until now, this power consumption has not been of great concern, since large packages, cooling fins fans, and fans have been capable of dissipating the generated heat. However, as the density and size of the chips and systems continue to increase, the difficulty in providing adequate cooling might either add significant cost to the system or provide a limit on the amount of functionality that can be provided. Thus, it is evident that methodologies for the design of high-throughput, low-power digital systems are needed. Samsung can provide a full range of low power services based on its success:

- Low power design methodologies from system-level to GDSII
- Consult low power strategies
- Low power flow setup
- Low power verification setup
- Power analysis service

If you require our ‘Low Power Design’ consultation service, please contact your Account Manager.
DFT
The reduction in feature size increases the probability that a manufacturing defect in the IC will result in a faulty chip. A very small defect can easily result in a faulty transistor or interconnecting wire when the feature size is less than 100nm. Furthermore, it takes only one faulty transistor or wire to make the entire chip fail to function properly or at the required operating frequency. Yet, defects created during the manufacturing process are unavoidable, and, as a result, some number of ICs is expected to be faulty; therefore, DFT is required to guarantee fault-free products, regardless of whether the product is a VLSI device or an electronic system composed of many VLSI devices. Samsung can provide full range of DFT consultations as below.

- Scan architecture specification
- Scan insertion with various EDA solutions
- Memory BIST integration with various EDA solutions
IP Merge Service
Samsung offers high-quality and silicon-proven IP solutions including Interface IP, Analog/Mixed Signal IP, Embedded Memory IP, and Specialty IP for all application. However, GDSII for some IPs cannot be provided to customers under IP licensing conditions. Samsung can offer IP merge service for those IPs as well as full-chip level physical verification with IP integrated. Also Samsung can offer phantom database for those IPs to help our customer go through physical verification and this can eliminate any potential iterations in physical verification caused by missing IPs.
Physical Verification
In nanometer technology, physical verification has become a sophisticated, multi-stage process that demands highly integrated approaches to the processing and handling of huge amounts of complex design data. Samsung can provide full range consultation service like below.In nanometer technology, physical verification has become a sophisticated, multi-stage process that demands highly integrated approaches to the processing and handling of huge amounts of complex design data.In nanometer technology, physical verification has become a sophisticated, multi-stage process that demands highly integrated approaches to the processing and handling of huge amounts of complex design data.

Physical Verification flow
- DRC (Design Rule Check)
- LVS (Layout Versus Schematic)
- PERC (Programmable Electrical Rule Check)
- DFM (Design For Manufacturing)
- Dummy fill insertion
- DPT (Double Patterning Technology)
DFM
As VLSI technologies scale toward the nanometer regime, manufacturability considerations pose the main threat to continued progress. Since circuit features of 45 nm or smaller are still fabricated using 193nm wavelength lithography, it is a formidable challenge to reliably print designed circuit layout onto silicon wafers. Even when the printing is successful, the circuit features on silicon are subject to remarkable process variations. Consequently, fabricated circuits often fail to satisfy design specifications. The manufacturability problem is so severe that it has to be addressed in design stages in addition to efforts in fabrication process development. Recently, design for manufacturability (DFM) has become a very active research area and Samsung can provide a variety of DFM kits / solutions.

- LFD (Litho Friendly Design)
- PM (Pattern Matching)
- MAS (Manufacturability Analysis Scoring)
- VIA
- VOS (VIA Optimization Solution)
- CMP (Chemical Mechanical Polishing)
Tape-out Review
Samsung offers ‘Tape-out Review’ to help our customer’s silicon success and faster time-to-market. Samsung can provide the following services:

- Sign-off criteria recommendations
- Tape-out review consultation
- IR, noise and timing analysis services
- Physical verification (DRC/LVS/PERC/DFM) services

If you require our ‘Tape-out Review’ consultation service, please contact your Account Manager.
ESD/EOS/Latchup Solutions
Samsung offers various types of ESD/EOS/Latchup services from chip design to evaluation. ESD/EOS/Latchup consulting is also available.

- ESD/Latchup reference guide documents
- Design verification infra: Schematic level & GDS level (BEOL/FEOL)
- Silicon-proven IO/ESD cell & ESD power clamp library
- IC-level ESD testing and failure analysis
- TLP testing and analysis
- System-level ESD/EOS consulting
- Factory-level ESD/EOS consulting including issues of IC/Module/Set assembly lines
PSI Solutions
The PSI solution service is a one-stop turnkey solution provider covering the full spectrum of services from basic PSI sign-off guidance to customer-defined platform PSI design guidance and also capable of consulting services to achieve the excellent customer satisfaction based on synergy of on/off chip optimization.

- PSI Signoff DM and application note
- Platform Design Support for Chip Validation
- Platform Design Guidance for Basic IPs (HSI, Memory I/F, Core PDN, etc.)
- Pre-/Post-layout PSI Analysis & Solution (Early-stage PSI Estimation, >10Gbps HSI IP Enabling, Analysis & Solution for PSI Optimization)
- Platform Design Support for Chip Validation (Function & Electrical Test)
Security Solutions
Samsung offers competitive security solution and consulting service for wide range of products including, not limited to application processors for smartphones, smart cards, automotive devices and IoT devices, etc.
Samsung Security is ready to provide optimized security solutions from hardware layer to application layer,including security requirement analysis, the high level of architecture design, consulting for certification and standard specification, and supply not only IP (Hardmacro/Softmacro IP) but also software specific solutions for customer.

- Security Requirement Analysis
- Security Architecture
- Security IP
- Certification & Standard
- Secure Key Provisioning
Analog Reference Design
Samsung offers high-quality and silicon-proven analog reference design including bandgapreference, voltage/current reference, current mirror, comparator, various op-amps, oscillator. Schematic and layout for analog reference design can be provided to customers under NDA conditions. In addition, Samsung can provide a user's guide to analog reference design, which helps customers pass solid designs.
Contents of Analog Reference Design
Analog Reference Design Description 14LPP 10LPP
Bandgap_Reference 1.8V VDD 1.2V Output Bandgap Reference O O
Voltage_Reference_Top_Level 1.8V VDD Top-Level Reference Voltage Generator O O
Voltage_Reference_Middle_Level 1.8V VDD Mid-Level Reference Voltage Generator O  
Voltage_Reference_Bottom_Level 1.8V VDD Bottom-Level Reference Voltage Generator O  
Current_Reference_EG_Sourcing_1uA 1.8V VDD EG PFET Current Reference for 1uA O  
Current_Reference_EG_Sourcing_3uA 1.8V VDD EG PFET Current Reference for 3uA   O
Current_Reference_EG_Sourcing_6uA 1.8V VDD EG PFET Current Reference for 6uA   O
Current_Reference_EG_Sourcing_9uA 1.8V VDD EG PFET Current Reference for 9uA   O
Current_Reference_EG_Sourcing_12uA 1.8V VDD EG PFET Current Reference for 12uA   O
Current_Reference_EG_Sinking_6uA 1.8V VDD EG NFET Current Reference for 6uA O  
CurrentMirror_EGN_2p5uA 1.8V VDD EG NFET type 2.5uA current mirror with unity current transfer ratio O O
CurrentMirror_EGN_10uA 1.8V VDD EG NFET type 10uA current mirror with unity current transfer ratio O O
CurrentMirror_EGN_20uA 1.8V VDD EG NFET type 20uA current mirror with unity current transfer ratio O O
CurrentMirror_EGP_2.5uA 1.8V VDD EG PFET type 2.5uA current mirror with unity current transfer ratio O O
CurrentMirror_EGP_10uA 1.8V VDD EG PFET type 10uA current mirror with unity current transfer ratio O O
4bit_MU-_EG EG FET type CMOS 4bit switch that blocks or passes a signal level from input to output O O
TransmissionGate_EG EG FET type CMOS switch that blocks or passes a signal level from input to output O O
Comparator_EG EG FET type circuit block that compares two voltages and outputs a digital signal indicating which is larger O O
1stage_Op_Amp_EG 1.8V VDD Single ended 1-stage Operational Amplifier O O
2stage_Op_Amp_EG 1.8V VDD Single ended 2-stage Operational Amplifier O  
Rail_to_Rail_Input_Amp_EG 1.8V VDD EG FET type Rail-to-Rail Input Operational Transconductance Amplifier (OTA) O  
Folded_Cascode_Op_Amp_EG 1.8V VDD EG FET type Folded-Cascode Operational Transconductance Amplifier (OTA) O O
Ring_Oscillator Ring type internal Oscillator (SG Transistor) O O
Frequency_Divider Clock divider circuit to make frequency down (1/8, 1/9) O O
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